Entry
TSE: Syntax: Highlight: What is a possible .syn file for VHDL? (TSE v2.8 / 3.0 / 4.0)
Jul 1st, 2003 08:28
Knud van Eeden,
// copyright Eliyahu Trigoub
// convert this to e.g. 'vhd.syn',
// see http://www.faqts.com/knowledge_base/view.phtml/aid/22932/fid/929
// and save it in your
// TSE .syn file directory '..\synhi\'
--- cut here ----------------------------------------------------------
wordset=0-9A-Z_a-z
HiliteIncompleteQuotes=TRUE
IgnoreCaseOfKeyWords=TRUE
HiliteIf0StyleComments=FALSE
Transparent=TRUE
CursorLineFlag=CursorLineOverrides
NumberFlag=Integer|Real|Comma
TillEOL1=--
TillEOLStartCol1=0
Quote1="
[KeyWords1]
access after alias all architecture array assert attribute begin
block body
buffer bus case component configuration constant disconnect downto
else elsif
end entity exit file for function generate generic group guarded if
impure in
inertial inout is label library linkage literal loop map new next
null of on
open others out package port postponed procedure process pure range
record
register reject report return select severity shared signal subtype
then to
transport type unaffected units until use variable wait when while
with
[KeyWords2]
& * + - / : < = > abs and mod nand nor not or rem rol ror sla sll sra
srl
xnor xor |
[KeyWords3]
ack append_mode bel bs can cr dc1 dc2 dc3 dc4 dle em enq eot error
esc etb
etx failure false ff fs fsp gsp hr ht lf min mode_error ms nak
name_error
note ns nul open_ok ps read_mode rsp sec si so soh status_error stx
sub syn
true us usp vt warning write_mode
[KeyWords4]
bit bit_vector boolean character delay_length file_open_kind
file_open_status
input integer line natural output positive real severity_level side
signed
small_int std_logic std_logic_vector std_ulogic std_ulogic_vector
string text
time unsigned ux01 ux01z width x01 x01z
[KeyWords5]
and_reduce conv_integer conv_signed conv_std_logic_vector
conv_unsigned
deallocate endfile eq ext falling_edge file_close file_open ge gt
hread
hwrite is_x le lt maximum minimum nand_reduce ne nor_reduce now
or_reduce
oread owrite read readline resolved rising_edge shl shr sign_extend
sxt
to_bit to_bitvector to_integer to_signed to_stdlogic to_stdlogicvector
to_stdulogic to_stdulogicvector to_unsigned to_ux01 to_x01 to_x01z
write
writeline xnor_reduce xor_reduce zero_extend
[KeyWords6]
'range active ascending base delayed driving driving_value event
foreign high
image instance_name last_active last_event last_value left leftof
length low
path_name pos pred quiet reverse_range right rightof simple_name
stable succ
transaction val value
[KeyWords7]
#
--- cut here ----------------------------------------------------------